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Electrical Engineering

Indian Institute of Technology Bombay

Electrical Engineering

Indian Institute of Technology Bombay

People

People

Faculty

Udayan Ganguly
Udayan Ganguly iit bombay
Qualifications

• Ph.D. Materials Science and Engineering Cornell University,2006
• M.S. Materials Science and Engineering Cornell University,2005
• B.Tech., Metallurgical Engineering Indian Institute of Technology Madras (IITM), 2000

Research Interests

• Memories – Resistance RAM, Charge Trap / Nanocrystal Flash Memory, Ferroelectric RAM Logic – Transistor variability, SOI-MOSFETs Architecture: Neuromorphic Algorithms and Circuit Implementations.

Work Experience

• April 2010-June 2010 Member of Technical Staff, FEP-Applied Materials
• Sept 2006- April 2010 Senior Application Development Engineer, FEP- Applied Materials
• May 2007- Oct 2007 Visiting Assistant Professor, Electrical Engineering, IIT Bombay
• May 2006- Aug 2006 Post Doctoral Scholar, NASA Ames Research Center
• Fall-2004, Graduate Research Intern, Intel Research, Manager: Dr. Yuegang Zhang

Journal Papers

  1. D. Khilwani, V. Moghe, S. Lashkare, V. Saraswat, P. Kumbhare, M. Shojaei Baghini, S. Jandhyala, S. Subramoney, and U. Ganguly, "PrxCa1?xMnO3 based stochastic neuron for Boltzmann machine to solve “maximum cut” problem", APL Materials, vol. 7, pp. 091112, Sep. 2019. [DOI]
  2. S. Lashkare, P. Kumbhare, V. Saraswat, and U. Ganguly, "Transient Joule Heating based Oscillator Neuron for Neuromorphic Computing", IEEE Electron Device Letters, pp. 1-1, Jul. 2018. [DOI]
  3. S. Lashkare, S. Chouhan, T. Chavan, A. Bhat, P. Kumbhare, and U. Ganguly, "PCMO RRAM for Integrate-and-Fire Neuron in Spiking Neural Networks", IEEE Electron Device Letters, vol. 39, pp. 484-487, Apr. 2018. [DOI]
  4. S. Lashkare, N. Panwar, P. Kumbhare, B. Das, and U. Ganguly, "PCMO-Based RRAM and NPN Bipolar Selector as Synapse for Energy Efficient STDP", IEEE Electron Device Letters, vol. 38, pp. 1212-1215, Sep. 2017. [DOI]
  5. P. Harsha Vardhan, Sushant Mittal, Swaroop Ganguly, and Udayan Ganguly, "Analytical Estimation of Threshold Voltage Variability by Metal Gate Granularity in FinFET", IEEE Transactions on Electron Devices, vol. 64, pp. 3071-3076, Aug. 2017. [DOI]
  6. Amita, S. Mittal, and U. Ganguly, "An Analytical Model to Estimate ${V}_{T}$ Distribution of Partially Correlated Fin Edges in FinFETs Due to Fin-Edge Roughness", IEEE Transactions on Electron Devices, vol. 64, pp. 1708-1715, Apr. 2017. [DOI]
  7. Bhaskar Das, Sushama Sushama, Jorg Schulze, and Udayan Ganguly, "Sub-0.2 V Impact Ionization in Si n-i-p-i-n Diode", IEEE Transactions on Electron Devices, vol. 63, pp. 4668-4673, Dec. 2016. [DOI]
  8. V. S. Senthil Srinivasan, B. Das, V. Sangwan, C. Pinto Gomez, M. Oehme, U. Ganguly, and J. Schulze, "Low temperature epitaxial germanium P+IN+IP+ selector for RRAM", 2015 73rd Annual Device Research Conference (DRC), Jun. 2015. [DOI]
  9. R. Mandapati, B. Das, V. Ostwal, and U. Ganguly, "Voltage Designability: An enabler for selector technology", 2014 14th Annual Non-Volatile Memory Technology Symposium (NVMTS), Oct. 2014. [DOI]
  10. R. Mandapati, S. Shrivastava, B. Das, Sushama, V. Ostwal, J. Schulze, and U. Ganguly, "High performance sub-430°C epitaxial silicon PIN selector for 3D RRAM", 72nd Device Research Conference, Jun. 2014. [DOI]
  11. B. Das, R. Meshram, V. Ostwal, J. Schulze, and U. Ganguly, "Observation of impact ionization at sub-0.5V and resultant improvement in ideality in I-NPN selector device by Si epitaxy for RRAM applications", 72nd Device Research Conference, Jun. 2014. [DOI]
  12. R. Meshram, B. Das, R. Mandapati, S. Lashkare, S. Deshmukh, S. Lodha, U. Ganguly, and J. Schulze, "High performance triangular barrier engineered NIPIN selector for bipolar RRAM", 2014 IEEE 6th International Memory Workshop (IMW), May 2014. [DOI]
  13. S. Mittal, S. Gupta, A. Nainani, M.C. Abraham, K. Schuegraf, S. Lodha, and U. Ganguly, "Epitaxially Defined (ED) FinFET: Variability Resistant and High Performance Technology", IEEE Transactions on Electron Devices, vol. 61, no. 8, pp. 2711-2718, 2014.
  14. V. P. Kishore, P. Paramahans, S. Sadana, U. Ganguly, and S. Lodha, "Nanocrystal-based Ohmic contacts on n and p-type germanium", Appl. Phys. Lett. 100, 2012.
  15. V. S. S. Srinivasan, S. Chopra, P. Karkare, P. Bafna, S. Lashkare, P. Kumbhare, Y. Kim, S. Srinivasan, S. Kuppurao, S. Lodha, and U. Ganguly, "Punch-through Diode based Bipolar RRAM Selector by Si Epitaxy", IEEE Electron Devices Letters, vol. 33, pp. 1396, 2012.
  16. U. Ganguly, T. Guarini, D. Wellekens, L. Date, Y. Cho, A. Rothschild, and J. Swenberg, "Impact of Top-Surface Tunnel Oxide Nitridation on Flash Memory Performance and Reliability", IEEE Electron Device Letters, vol. 31, pp. 123-125, 2010.
  17. C. Sandhya, A. B. Oak, N. Chattar, U. Ganguly, C. Olsen, S. M. Seutter, L. Date, R. Hung, J. Vasi, and and S. Mahapatra, "Study of Endurance Induced Degradation Mechanism in SANOS Memories under NAND (FN/FN) Operation", under review,, IEEE Transactions on Electron Devices, 2010.
  18. C. Sandhya, U. Ganguly, N. Chattar, C. Olsen, S. M. Seutter, L. Date, R. Hung, J. Vasi, and S. Mahapatra, "Effect of SiN on Performance and Reliability of Charge Trap Flash (CTF) Under Fowler Nordheim Tunneling Program/Erase Operation", IEEE Electron Device Letters, vol. 30, pp. 171-173, 2009.
  19. C. Sandhya, A. B. Oak, A.S. Joshi, N. Chattar, U. Ganguly, C. Olsen, S. M. Seutter, L. Date, R. Hung, J. Vasi, and and S. Mahapatra, "Impact of SiN Composition Variation on SANOS Memory Performance and Reliability under NAND (FN/FN) Operation", IEEE Transactions on Electron Devices, vol. 56, pp. 3123-3132, 2009.
  20. U. Ganguly, T.-H. Hou, and E. C. Kan, "Enhanced Electrostatics for Low-Voltage Operations in Nanocrystal based Nanotube/Nanowire Memories", IEEE Trans. Nanotechnology, 2007.
  21. T.-H. Hou, U. Ganguly, and and E. C. Kan, "Fermi-Level Pinning in Nanocrystal Memories", IEEE Electron Device Letters, vol. 28, 2007.
  22. T. -H. Hou, C. Lee, V. Narayanan, U. Ganguly, and E. C. Kan, "Design Optimization of Metal Nanocrystal Memory—Part II: Gate-Stack Engineering", IEEE Transactions on Electron Devices, vol. 53, 2006.
  23. J. Guo, E. C. Kan, U. Ganguly, and Y. Zhang, "High Sensitivity and Non-Linearity of Carbon-Nanotube-Based Charge Sensors", Journal of Applied Physics, vol. 99, 2006.
  24. U. Ganguly, V. Narayanan, C. Lee, T.-H. Hou, and E. C. Kan, "Three dimensional analytical modeling of nanocrystal memory electrostatics", Journal of Applied Physics, 2006.
  25. T.-H. Hou, U. Ganguly, and E. C. Kan, "Programmable Molecular Orbital States of C60 from Integrated Circuits", Applied Physics Letters, vol. 89, 2006.
  26. C. Lee, U. Ganguly, V. Narayanan, T.-H Hou, and E. C. Kan, "Asymmetric Electric Field Enhancement in Nanocrystal Memories", IEEE Electron Device Letters, vol. 26, 2005.
  27. U. Ganguly, E.C. Kan, and Y. Zhang, "Carbon nanotube FET memory with charge storage in metal nanocrystal", Applied Physics Letters, vol. 87, 2005.
  28. U. Ganguly and J. P. Krusius, "Novel compensation CMP for low dishing and high global planarity for ultra-planar die applications in micro-optics and MEMS", Thin Solid Films, vol. 460, 2004.
  29. U. Ganguly and J. P. Krusius, "Fabrication of Ultra-Planar Aluminum Mirror Array by Novel Encapsulation CMP for Micro-optics and MEMS applications", Journal of Electrochemical Society, vol. 151, 2004.
Conference Papers / Book Chapters
  1. P Harsha Vardhan, Sushant Mittal, A. S. Shekhawat, Swaroop Ganguly, and Udayan Ganguly, "Analytical modeling of metal gate granularity induced V_t variability in NWFETs" in 2016 74th Annual Device Research Conference (DRC), IEEE, Jun. 2016. [DOI]
  2. P Harsha Vardhan, Sushant Mittal, A. S. Shekhawat, S. Ganguly, and U.Ganguly, "Analytical modeling of Metal gate granularity induced Vt variability in NWFETs" in 74th Device Research Conference, Newark, Jun. 2016.
  3. P. Debashis, S. Mittal, S. Lodha, and U. Ganguly, "Dopant Deactivation: A new challenge in sub-20nm Scaled FinFETs" in IEEE VLSI-TSA Hsinchu Taiwan, Apr. 2014.
  4. S. Mittal, P. Debashis, A. Nainani, M. C. Abraham, S. Lodha, and U. Ganguly, " Epi Defined (ED) FinFET with Dynamic Threshold: Reduced VT Variability, Enhanced Performance, and a novel Multiple VT" in IEEE INDICON, Best paper award, Dec. 2013.
  5. U. Ganguly, Y. Yokota, J. Tang, S. Sun, M. Rogers, M. Jin , K. Thadani, H. Hamana, G. Leung, B. Chandrasekaran, S. Thirupapuliyur, C. Olsen, V. Nguyen, and S. Srinivasan, "Scalability Enhancement of FG NAND by FG Shape Modification" in International Memory Workshop, Dec. 2010.
  6. C. Sandhya, U. Ganguly, B. Apoorva, C. Olsen, S. Seutter, L. Date, R. Hung, J. Vasi, and S. Mahapatra, "Influence of SiN composition on Program and Erase Characteristics of SANOS-type Flash Memories" in IEEE Intl. Workshop on Electron Devices and Semiconductor Technology (IEDST), Received the Outstanding Paper Award, Dec. 2009.
  7. Sandhya C., U. Ganguly, K.K. Singh, P.K. Singh, R. Hung, C. Olsen, S. M. Seutter, G. Conti, K. Ahmed andN. Krishna, J. Vasi, and and S. Mahapatra, "The Effect of Band Gap Engineering of the Nitride Storage Node on Performance and Reliability of Charge Trap Flash" in International Physics of Failure Analysis (IPFA), Dec. 2008.
  8. Sandhya C., U. Ganguly, K.K. Singh, P.K. Singh, C. Olsen, S. M. Seutter, R. Hung, G. Conti, K. Ahmed, N. Krishna, J. Vasi and S. Mahapatra, "Nitride Engineering and the effect of interfaces on charge trap flash performance and reliability" in International Reliability Physics Symposium (IRPS), Dec. 2008.
  9. A. Nainani, S. Palit, P. K. Singh, U. Ganguly, N. Krishna, J. Vasi and S. Mahapatra, "Development of a 3D simulator for metal nanocrystal flash memories under NAND operation" in International Electron Devices Meeting (IEDM), Dec. 2007.
  10. U. Ganguly, T.-H. Hou, and E. C. Kan, "Process Integration of Composite High-k Tunneling Dielectric for Nanocrystal Based Carbon Nanotube Memory" in Material Research Symposium, Dec. 2006.
  11. U. Ganguly, J. Guo, E. C. Kan, and Y. Zhang, "Carbon nanotubes based non-volatile memory and charge sensors" in Proc. of SPIE Conference, Invited paper, Dec. 2005.
  12. U. Ganguly, C. Lee, and E. C. Kan, "Retention characteristics for nonvolatile memory based on metal nanocrystals and carbon nanotube FET with CVD SiO2 and ALD HfO2 tunneling dielectrics" in Material Research Symposium, Dec. 2005.
  13. U. Ganguly, T.-H. Hou, and E. C. Kan, "Quantum Transport and Trap Effects in Tunneling Rate Measurements of Metal Nanocrystal Based Carbon Nanotube Memory" in Material Research Symposium, Dec. 2005.
  14. U. Ganguly, C. Lee, and E. C. Kan, "Experimental Observation of Non-Volatile Charge Injection and Molecular Redox in Fullerenes C60 and C70 in an EEPROM Type Device" in Material Research Symposium, MRS Trophy Award for best paper in Symposium D, Dec. 2004.
  15. C. Lee, U. Ganguly, and E. C. Kan, "Characterization of Number Fluctuations in Gate-last Metal Nanocrystal Nonvolatile Memory Array Beyond 90nm CMOS Technology" in Material Research Symposium, Dec. 2004.
  16. U. Ganguly, C. Lee, and E. C. Kan, "Interface and oxide contamination monitoring in integration of fullerenes and carbon nanotubes with aggressively scaled CMOS gate stacks" in Material Research Symposium, Dec. 2003.

Address

  • Office Room No: NanoE 605, Department of Electrical Engineering
    IIT Bombay, Powai
    Mumbai 400 076, India

  • (O): +91-22-2576-7698
  • udayan@ee.iitb.ac.in
  • Visit Website
Udayan Ganguly iit bombay
Udayan Ganguly
Qualifications

• Ph.D. Materials Science and Engineering Cornell University,2006
• M.S. Materials Science and Engineering Cornell University,2005
• B.Tech., Metallurgical Engineering Indian Institute of Technology Madras (IITM), 2000

Research Interests

• Memories – Resistance RAM, Charge Trap / Nanocrystal Flash Memory, Ferroelectric RAM Logic – Transistor variability, SOI-MOSFETs Architecture: Neuromorphic Algorithms and Circuit Implementations.

Work Experience

• April 2010-June 2010 Member of Technical Staff, FEP-Applied Materials
• Sept 2006- April 2010 Senior Application Development Engineer, FEP- Applied Materials
• May 2007- Oct 2007 Visiting Assistant Professor, Electrical Engineering, IIT Bombay
• May 2006- Aug 2006 Post Doctoral Scholar, NASA Ames Research Center
• Fall-2004, Graduate Research Intern, Intel Research, Manager: Dr. Yuegang Zhang

Journal Papers

  1. D. Khilwani, V. Moghe, S. Lashkare, V. Saraswat, P. Kumbhare, M. Shojaei Baghini, S. Jandhyala, S. Subramoney, and U. Ganguly, "PrxCa1?xMnO3 based stochastic neuron for Boltzmann machine to solve “maximum cut” problem", APL Materials, vol. 7, pp. 091112, Sep. 2019. [DOI]
  2. S. Lashkare, P. Kumbhare, V. Saraswat, and U. Ganguly, "Transient Joule Heating based Oscillator Neuron for Neuromorphic Computing", IEEE Electron Device Letters, pp. 1-1, Jul. 2018. [DOI]
  3. S. Lashkare, S. Chouhan, T. Chavan, A. Bhat, P. Kumbhare, and U. Ganguly, "PCMO RRAM for Integrate-and-Fire Neuron in Spiking Neural Networks", IEEE Electron Device Letters, vol. 39, pp. 484-487, Apr. 2018. [DOI]
  4. S. Lashkare, N. Panwar, P. Kumbhare, B. Das, and U. Ganguly, "PCMO-Based RRAM and NPN Bipolar Selector as Synapse for Energy Efficient STDP", IEEE Electron Device Letters, vol. 38, pp. 1212-1215, Sep. 2017. [DOI]
  5. P. Harsha Vardhan, Sushant Mittal, Swaroop Ganguly, and Udayan Ganguly, "Analytical Estimation of Threshold Voltage Variability by Metal Gate Granularity in FinFET", IEEE Transactions on Electron Devices, vol. 64, pp. 3071-3076, Aug. 2017. [DOI]
  6. Amita, S. Mittal, and U. Ganguly, "An Analytical Model to Estimate ${V}_{T}$ Distribution of Partially Correlated Fin Edges in FinFETs Due to Fin-Edge Roughness", IEEE Transactions on Electron Devices, vol. 64, pp. 1708-1715, Apr. 2017. [DOI]
  7. Bhaskar Das, Sushama Sushama, Jorg Schulze, and Udayan Ganguly, "Sub-0.2 V Impact Ionization in Si n-i-p-i-n Diode", IEEE Transactions on Electron Devices, vol. 63, pp. 4668-4673, Dec. 2016. [DOI]
  8. V. S. Senthil Srinivasan, B. Das, V. Sangwan, C. Pinto Gomez, M. Oehme, U. Ganguly, and J. Schulze, "Low temperature epitaxial germanium P+IN+IP+ selector for RRAM", 2015 73rd Annual Device Research Conference (DRC), Jun. 2015. [DOI]
  9. R. Mandapati, B. Das, V. Ostwal, and U. Ganguly, "Voltage Designability: An enabler for selector technology", 2014 14th Annual Non-Volatile Memory Technology Symposium (NVMTS), Oct. 2014. [DOI]
  10. R. Mandapati, S. Shrivastava, B. Das, Sushama, V. Ostwal, J. Schulze, and U. Ganguly, "High performance sub-430°C epitaxial silicon PIN selector for 3D RRAM", 72nd Device Research Conference, Jun. 2014. [DOI]
  11. B. Das, R. Meshram, V. Ostwal, J. Schulze, and U. Ganguly, "Observation of impact ionization at sub-0.5V and resultant improvement in ideality in I-NPN selector device by Si epitaxy for RRAM applications", 72nd Device Research Conference, Jun. 2014. [DOI]
  12. R. Meshram, B. Das, R. Mandapati, S. Lashkare, S. Deshmukh, S. Lodha, U. Ganguly, and J. Schulze, "High performance triangular barrier engineered NIPIN selector for bipolar RRAM", 2014 IEEE 6th International Memory Workshop (IMW), May 2014. [DOI]
  13. S. Mittal, S. Gupta, A. Nainani, M.C. Abraham, K. Schuegraf, S. Lodha, and U. Ganguly, "Epitaxially Defined (ED) FinFET: Variability Resistant and High Performance Technology", IEEE Transactions on Electron Devices, vol. 61, no. 8, pp. 2711-2718, 2014.
  14. V. P. Kishore, P. Paramahans, S. Sadana, U. Ganguly, and S. Lodha, "Nanocrystal-based Ohmic contacts on n and p-type germanium", Appl. Phys. Lett. 100, 2012.
  15. V. S. S. Srinivasan, S. Chopra, P. Karkare, P. Bafna, S. Lashkare, P. Kumbhare, Y. Kim, S. Srinivasan, S. Kuppurao, S. Lodha, and U. Ganguly, "Punch-through Diode based Bipolar RRAM Selector by Si Epitaxy", IEEE Electron Devices Letters, vol. 33, pp. 1396, 2012.
  16. U. Ganguly, T. Guarini, D. Wellekens, L. Date, Y. Cho, A. Rothschild, and J. Swenberg, "Impact of Top-Surface Tunnel Oxide Nitridation on Flash Memory Performance and Reliability", IEEE Electron Device Letters, vol. 31, pp. 123-125, 2010.
  17. C. Sandhya, A. B. Oak, N. Chattar, U. Ganguly, C. Olsen, S. M. Seutter, L. Date, R. Hung, J. Vasi, and and S. Mahapatra, "Study of Endurance Induced Degradation Mechanism in SANOS Memories under NAND (FN/FN) Operation", under review,, IEEE Transactions on Electron Devices, 2010.
  18. C. Sandhya, U. Ganguly, N. Chattar, C. Olsen, S. M. Seutter, L. Date, R. Hung, J. Vasi, and S. Mahapatra, "Effect of SiN on Performance and Reliability of Charge Trap Flash (CTF) Under Fowler Nordheim Tunneling Program/Erase Operation", IEEE Electron Device Letters, vol. 30, pp. 171-173, 2009.
  19. C. Sandhya, A. B. Oak, A.S. Joshi, N. Chattar, U. Ganguly, C. Olsen, S. M. Seutter, L. Date, R. Hung, J. Vasi, and and S. Mahapatra, "Impact of SiN Composition Variation on SANOS Memory Performance and Reliability under NAND (FN/FN) Operation", IEEE Transactions on Electron Devices, vol. 56, pp. 3123-3132, 2009.
  20. U. Ganguly, T.-H. Hou, and E. C. Kan, "Enhanced Electrostatics for Low-Voltage Operations in Nanocrystal based Nanotube/Nanowire Memories", IEEE Trans. Nanotechnology, 2007.
  21. T.-H. Hou, U. Ganguly, and and E. C. Kan, "Fermi-Level Pinning in Nanocrystal Memories", IEEE Electron Device Letters, vol. 28, 2007.
  22. T. -H. Hou, C. Lee, V. Narayanan, U. Ganguly, and E. C. Kan, "Design Optimization of Metal Nanocrystal Memory—Part II: Gate-Stack Engineering", IEEE Transactions on Electron Devices, vol. 53, 2006.
  23. J. Guo, E. C. Kan, U. Ganguly, and Y. Zhang, "High Sensitivity and Non-Linearity of Carbon-Nanotube-Based Charge Sensors", Journal of Applied Physics, vol. 99, 2006.
  24. U. Ganguly, V. Narayanan, C. Lee, T.-H. Hou, and E. C. Kan, "Three dimensional analytical modeling of nanocrystal memory electrostatics", Journal of Applied Physics, 2006.
  25. T.-H. Hou, U. Ganguly, and E. C. Kan, "Programmable Molecular Orbital States of C60 from Integrated Circuits", Applied Physics Letters, vol. 89, 2006.
  26. C. Lee, U. Ganguly, V. Narayanan, T.-H Hou, and E. C. Kan, "Asymmetric Electric Field Enhancement in Nanocrystal Memories", IEEE Electron Device Letters, vol. 26, 2005.
  27. U. Ganguly, E.C. Kan, and Y. Zhang, "Carbon nanotube FET memory with charge storage in metal nanocrystal", Applied Physics Letters, vol. 87, 2005.
  28. U. Ganguly and J. P. Krusius, "Novel compensation CMP for low dishing and high global planarity for ultra-planar die applications in micro-optics and MEMS", Thin Solid Films, vol. 460, 2004.
  29. U. Ganguly and J. P. Krusius, "Fabrication of Ultra-Planar Aluminum Mirror Array by Novel Encapsulation CMP for Micro-optics and MEMS applications", Journal of Electrochemical Society, vol. 151, 2004.
Conference Papers / Book Chapters
  1. P Harsha Vardhan, Sushant Mittal, A. S. Shekhawat, Swaroop Ganguly, and Udayan Ganguly, "Analytical modeling of metal gate granularity induced V_t variability in NWFETs" in 2016 74th Annual Device Research Conference (DRC), IEEE, Jun. 2016. [DOI]
  2. P Harsha Vardhan, Sushant Mittal, A. S. Shekhawat, S. Ganguly, and U.Ganguly, "Analytical modeling of Metal gate granularity induced Vt variability in NWFETs" in 74th Device Research Conference, Newark, Jun. 2016.
  3. P. Debashis, S. Mittal, S. Lodha, and U. Ganguly, "Dopant Deactivation: A new challenge in sub-20nm Scaled FinFETs" in IEEE VLSI-TSA Hsinchu Taiwan, Apr. 2014.
  4. S. Mittal, P. Debashis, A. Nainani, M. C. Abraham, S. Lodha, and U. Ganguly, " Epi Defined (ED) FinFET with Dynamic Threshold: Reduced VT Variability, Enhanced Performance, and a novel Multiple VT" in IEEE INDICON, Best paper award, Dec. 2013.
  5. U. Ganguly, Y. Yokota, J. Tang, S. Sun, M. Rogers, M. Jin , K. Thadani, H. Hamana, G. Leung, B. Chandrasekaran, S. Thirupapuliyur, C. Olsen, V. Nguyen, and S. Srinivasan, "Scalability Enhancement of FG NAND by FG Shape Modification" in International Memory Workshop, Dec. 2010.
  6. C. Sandhya, U. Ganguly, B. Apoorva, C. Olsen, S. Seutter, L. Date, R. Hung, J. Vasi, and S. Mahapatra, "Influence of SiN composition on Program and Erase Characteristics of SANOS-type Flash Memories" in IEEE Intl. Workshop on Electron Devices and Semiconductor Technology (IEDST), Received the Outstanding Paper Award, Dec. 2009.
  7. Sandhya C., U. Ganguly, K.K. Singh, P.K. Singh, R. Hung, C. Olsen, S. M. Seutter, G. Conti, K. Ahmed andN. Krishna, J. Vasi, and and S. Mahapatra, "The Effect of Band Gap Engineering of the Nitride Storage Node on Performance and Reliability of Charge Trap Flash" in International Physics of Failure Analysis (IPFA), Dec. 2008.
  8. Sandhya C., U. Ganguly, K.K. Singh, P.K. Singh, C. Olsen, S. M. Seutter, R. Hung, G. Conti, K. Ahmed, N. Krishna, J. Vasi and S. Mahapatra, "Nitride Engineering and the effect of interfaces on charge trap flash performance and reliability" in International Reliability Physics Symposium (IRPS), Dec. 2008.
  9. A. Nainani, S. Palit, P. K. Singh, U. Ganguly, N. Krishna, J. Vasi and S. Mahapatra, "Development of a 3D simulator for metal nanocrystal flash memories under NAND operation" in International Electron Devices Meeting (IEDM), Dec. 2007.
  10. U. Ganguly, T.-H. Hou, and E. C. Kan, "Process Integration of Composite High-k Tunneling Dielectric for Nanocrystal Based Carbon Nanotube Memory" in Material Research Symposium, Dec. 2006.
  11. U. Ganguly, J. Guo, E. C. Kan, and Y. Zhang, "Carbon nanotubes based non-volatile memory and charge sensors" in Proc. of SPIE Conference, Invited paper, Dec. 2005.
  12. U. Ganguly, C. Lee, and E. C. Kan, "Retention characteristics for nonvolatile memory based on metal nanocrystals and carbon nanotube FET with CVD SiO2 and ALD HfO2 tunneling dielectrics" in Material Research Symposium, Dec. 2005.
  13. U. Ganguly, T.-H. Hou, and E. C. Kan, "Quantum Transport and Trap Effects in Tunneling Rate Measurements of Metal Nanocrystal Based Carbon Nanotube Memory" in Material Research Symposium, Dec. 2005.
  14. U. Ganguly, C. Lee, and E. C. Kan, "Experimental Observation of Non-Volatile Charge Injection and Molecular Redox in Fullerenes C60 and C70 in an EEPROM Type Device" in Material Research Symposium, MRS Trophy Award for best paper in Symposium D, Dec. 2004.
  15. C. Lee, U. Ganguly, and E. C. Kan, "Characterization of Number Fluctuations in Gate-last Metal Nanocrystal Nonvolatile Memory Array Beyond 90nm CMOS Technology" in Material Research Symposium, Dec. 2004.
  16. U. Ganguly, C. Lee, and E. C. Kan, "Interface and oxide contamination monitoring in integration of fullerenes and carbon nanotubes with aggressively scaled CMOS gate stacks" in Material Research Symposium, Dec. 2003.

Address

  • Office Room No: NanoE 605, Department of Electrical Engineering
    IIT Bombay, Powai
    Mumbai 400 076, India

  • (O): +91-22-2576-7698
  • udayan@ee.iitb.ac.in
  • Visit Website

  • Office Room No: NanoE 605, Department of Electrical Engineering
    IIT Bombay, Powai
    Mumbai 400 076, India

  • (O): +91-22-2576-7698
  • udayan@ee.iitb.ac.in
  • Visit Website

IIT Bombay was established in the year 1957 and the department of Electrical Engineering (EE) has been one of its major departments since its inception.

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IIT Bombay was established in the year 1957 and the department of Electrical Engineering (EE) has been one of its major departments since its inception.

Links

Contact Us

Follow US

Linkedin Facebook Twitter Instagram

IIT Bombay was established in the year 1957 and the department of Electrical Engineering (EE) has been one of its major departments since its inception.

Links

Contact Us

Follow Us

Linkedin Facebook Twitter Instagram
About | IITBEducation | Research | Site Map | Feedback | RTI | Contact Us

© 2023, IITB. All rights reserved.

About | IITBEducation | Research | Site Map | Feedback | RTI | Contact Us

© , IITB. All rights reserved.

About | IITBEducation | Research | Site Map | Feedback | RTI | Contact Us

© 2023, IITB. All rights reserved.