CMOS: Behaviour & Spice Modeling, Layout/Stick Diagram, Interconnects: Wireline models, CMOS Inverter, Static CMOS Logic gate design, Dynamic CMOS logic design, CMOS sequential logic design, Custom/Semi-custom ASIC Design, Design of standard cells, Standard Cell Library, Standard cell views and their creation (.v/.vhd, .lef, .lib, .gdsII, .spice), IO Library, IP libraries: Adders, Multipliers, Introduction to Memory, 6T cell based SRAM Design (single port and dual port), 8T cell based register file design, Timing Issues in Digital Circuits, Design Synthesis, Physical Design, Clock tree synthesis & Static Timing Analysis, RTL to gdsII design use cases and optimization using OpenLane based open source design flow.

Text/References:

1) Rabaey, Chandrakasan, Nikolic “Digital Integrated Circuits – A Design perspective,” Pearson 2nd Edition. 
2) N Weste and D Harris “CMOS VLSI Design: A Circuits and Systems Perspective,” 4th edition 
3) OpenLane Documentation
4) SkyWater SKY130 PDK Documentation 5) Efabless Caravel SoC Documentation