Overview Superscalar and VLIW architectures. Limits of instruction-level parallelism (ILP). Simultaneous multi-threaded (SMT) architecture, Performance enhancement through branch prediction and value prediction, BulkSMT, Thread level speculation. Run ahead execution, proactive instruction fetch, Multi-core architectures, data marshalling for multi-core architectures, power-constrained CMPs, heterogeneous core design, Core Fusion, Transactional memories. Performance evaluation of complex microarchitectures. On-chip interconnects (Network-on-Chip). Architectural vulnerabilities and reliable architectures. Patchable design. Secure architectures. Energy-efficient architectures. Power management. Cache design, energy-efficient cache partitioning, fast thread migration, thread throttling.