I. Transmission lines
a) Lossless/lossy transmission lines.
b) S-parameters, impedance matching.
c) Pulse propagation in transmission lines.
d) Even mode, odd mode (coupled/differential transmission lines).

II. Clocking in serial links
a) Asynchronous vs. synchronous links (serial links with low transfer rates).
b) Plesiochronous vs. Mesochronous systems.
c) Overview of high-speed serializers and deserializers.

III. Eye diagrams and BER estimation (based on eye quality factor).

IV. Phase-locked loops (PLLs) and delay-locked loops (DLLs)
a) Building blocks.
b) Loop analysis.
c) A brief overview of non-idealities in the PLLs/DLLs.
d) Jitter and phase noise (and relationship between them).
e) Jitter transfer functions in DLLs and PLLs.
f) BER estimation based on jitter.

V. Clock and data recovery (CDR) / deserializers
a) Phase detectors (linear/non-linear, full-rate/nth-rate etc.) and some examples.
b) Basic circuit-level blocks: Latches, flip-flops, XOR gates, muxes etc. in Current Mode Logic (CML).
c) Circuit level bandwidth enhancement techniques.
d) Tunable delays using tunable delay cells and phase interpolators.
e) Voltage controlled oscillators (VCOs).
f) Multi-phase clock generation.
g) CDR architectures

VI. Equalization and equalizers
a) Channel model and inter-symbol-interference (ISI).
b) Pre-cursor and post-cursor ISI.
c) Analog domain equalizers
i. CTLE (continuous time linear equalizers).
ii. FFE (feed-forward equalizers).
iii. Non-linear equalizers (decision-feedback equalizers).
d) Equalization in the digital domain.
e) Equalizer training and blind equalization techniques.
f) Eye monitor circuits for equalizers.

VII. Transmitters and serializers
a) Block diagram of a serializer.
b) LVDS (low-voltage differential signalling) and impedance matching.
c) Pre-emphasis (FIR) equalization for transmitters.

VIII. Other topics
a) Achieving higher speeds using m-PAM signalling.
b) Line coding with examples (such as 8b-10b, 64b-66b).
c) Multi-l