Journal Papers

1. Narasimhulu, K. Desai, M.P. Narendra, S.G. Rao, and V.R., "The effect of LAC doping on deep submicrometer transistor capacitances and its influence on device RF performance", IEEE Transactions on Electron Devices, 2004.
2. B. Anand, M.P. Desai, and V.R. Rao, "Silicon film thickness optimization for SOI-DTMOS from circuit performance considerations", IEEE Electron Device Letters, 2004.
3. Madhav Desai, Ritu Gupta, Abhay Karandikar, Kshitiz Saxena, and Vinayak Samant, "Reconfigurable Finite State Machine based IP Address Lookup for High Speed Routers", IEEE Journal on Selected Areas in Communications, vol. 21, no. 4, pp. 501-512, May 2003.
4. M. Desai, R. Gupta, A. Karandikar, K. Saxena, and V. Samant, "Reconfigurable finite-state machine based IP lookup engine for high-speed router", IEEEarticle on Selected Areas in Communications, May 2003.
5. N. Mohapatra, M. Desai, S. Narendra, and V.R. Rao, "Modeling of parasitic capacitances in deep submicrometer conventional and high-K dielectric MOS transistors", IEEE Transactions on Electron Devices, Apr. 2003.
6. M. P. Desai, H. Narayanan, S. Patkar, "The Realization of Finite State Machines by Decomposition and the Principal Lattice of Partitions of a Submodular Function", Special Issue on Submodular Functions, Discrete Applied Maths, 131, pp. 299-310, 2003.
7. Desai, M. Manjunath, and D., "On the connectivity in finite ad hoc networks", IEEE Communications Letters, Oct 2002.
8. P. Sivaram, B. Anand, and M. Desai, "Silicon film thickness considerations in SOI-DTMOS", IEEE Electron Device Letters, 2002.
9. Mohapatra, N.R., Desai, M.P., Narendra, S.G., Rao, and V.R., "The effect of high-K gate dielectrics on deep submicrometer CMOSdevice and circuit performance", IEEE Transactions on Electron Devices, 2002.
10. M.P. Desai, "Some results characterizing the finite time behaviour of the simulated annealing algorithm", Sadhana, vol. 24, pp. 317-337, 1999.
11. M.P. Desai and VB Rao, "Finite-Time Behavior of Slowly Cooled Annealing Chains", Probability in the Engineering and Informational Sciences, 1997.
12. M.P. Desai and V.B. Rao, "A characterization of the smallest eigenvalue of a graph", article of Graph Theory, vol. Volume 18, no. Issue 2, Mar. 1994.
13. M Desai, S Kumar, and PR Kumar, "Quasi-Statically Cooled Markov Chains", Probability in the Engineering and Informational Sciences, 1994.
14. Madhav P. Desai and Vasant B. Rao, "On the convergence of reversible Markov chains", SIAMarticle on Matrix Analysis and Applications, vol. Volume 14, no. Issue 4, Oct. 1993.
15. M. Desai and I. Hajj, "On the convergence of block relaxation methods for circuit simulation", IEEE Transactions on Circuits and Systems, Jul. 1989.
16. M. Desai and I. Hajj, "On the convergence of block relaxation methods for circuit simulation", IEEE Transactions on Circuits and Systems, Jul. 1989.

1. G. Hazari, S. Gangam, and M.P. Desai, "Bottleneck Identification Techniques Leading to Simplified Performance Models for Efficient Design Space Exploration in VLSI Memory Systems" in 23rd International Conference on VLSI Design pp ___, Dec. 2010.
2. S. Sahasrabuddhe, S. Sreenivasan, K. Ghosh, K. Arya, and M.P. Desai, "A C-to-RTL flow as an energy efficient alternative to the use of embedded processors in digital systems" in 13th EUROMICRO Conf. on Digital System Design, Dec. 2010.
3. P. Kumar and M.P. Desai, "Learning based address mapping for improving the performance of memory subsystems" in MASCOTS 2009, Dec. 2009.
4. G. Hazari, H. Kasture, and M.P. Desai, "On the Impact of Address Space Assignment on Performance in Systems-on-Chip" in 20th International Conference on VLSI Design, Dec. 2007.
5. Gaurav Trivedi, Madhav P. Desai and H. Narayanan, " Fast DC Analysis and its Application to Combinatorial Optimization Problems" in 19th International Conference on VLSI Design, pp.695-700, Dec. 2006.
6. V. Prasad and M. Desai, "On buffering schemes for long multi-layer nets" in Proceedings of the 17th IEEE International Conference on VLSI Design, Dec. 2005.
7. Madhav Desai and D. Manjunath, "On Range Matrices and Wireless Networks in d Dimensions" in Third International Symposium on Modeling and Optimization in Mobile, Ad Hoc, and Wireless Networks (WiOpt05), Dec. 2005.
8. G.T. Hazari, M.P. Desai, A. Gupta, , and S. Chakraborty, "A novel technique towards eliminating the global clock in VLSI circuits" in 17th International Conference on VLSI Design, Dec. 2004.
9. A. Mittal and M. Desai, "A distributed and pipelined controller for a modular and scalable hardware emulator" in 17th International Conference on VLSI Design, Dec. 2004.
10. Prasad, V. Desai, and M.P., "Interconnect delay minimization using a novel pre-mid-post buffer strategy" in 16th International Conference on VLSI Design, Dec. 2003.
11. M.S. Baghini and M.P. Desai, "Impact of technology scaling on metastability performance of CMOS synchronizing latches" in 15th International Conference on VLSI Design, Dec. 2002.
12. M. Shojaei Baghini and M. P. Desai, "Impact of technology scaling on metastability performance of of CMOS synchronizing latches" in IEEE International Conf. on VLSI Design, India, (Sister Conf. of IEEE DAC, DATE and ICCAD), pp.317 - 322 , Jan. 2002.
13. N. Mohapatra, M. Desai, S. Narendra, and V. R. Rao, "Impact of High-K Gate Dielectrics on Sub 100 nm CMOS Circuit Performance" in 31st European Solid-State Device Research Conference, Dec. 2001.
14. A. P. Nair, A. Gupta, and M. Desai, "An On-Chip Coupling Capacitance Measurement Technique" in 14th International Conference on VLSI Design, Dec. 2001.
15. R. Shelar, H. Narayanan and M. P. Desai, " Orthogonal Partitioning and Gated Clock Architecture for Low Power Realization of FSMs" in Proceedings of the 13th Annual IEEE International ASIC/SOC Conference, Washington, pp.266-270, Sep. 2000.
16. R. Shelar, M. P. Desai and H. Narayanan, " Decomposition of Finite State Machines for Area, Delay minimization" in Proceedings of the IEEE International Conference on Computer Design, Austin, Texas, USA, Dec. 1999.
17. H. Narayanan B. N. V. M. Gupta and M. P. Desai, "A state assignment scheme targeting performance and area" in Proceedings of 12th international conference in VLSI design, pp.378-383, Jan. 1999.