Journal Papers

1. Newton, Sujit, Suhit Pai, Virendra Singh, "DAAIP: Deadblock Aware Adaptive Insertion Policy for High Performance Caching", ICCD, Nov. 2017. [DOI]
2. Nihar Hage, Rohini Gulve, Masahiro Fujita, and Virendra Singh, "Instruction-based self-test for delay faults maximizing operating temperature", 2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS), Jul. 2017. [DOI]
3. Virendra Singh, Michiko Inoue, Kewal K. Saluja, and Hideo Fujiwara, "Instruction-Based Self-Testing of Delay Faults in Pipelined Processors", IEEE Trans. on VLSI Systems, vol. 14, no. 11, Nov. 2006.
4. Michiko Inoue, Kazuko Kambe, Virendra Singh, and Hideo Fujiwara, "Software-Based Self-Test of Processors for Stuck-at Faults and Path Delay Faults", Trans. of IEICE (DI), Jun. 2005.
5. Virendra Singh, Michiko Inoue, Kewal K. Saluja, and Hideo Fujiwara, "Delay Fault Testing of Processor Cores in Functional Mode", IEICE Trans. on Information & Systems, vol. J88-D-I, Mar. 2005.

1. Nihar Hage, Satyadev Ahlawat, and Virendra Singh, "In-situ Monitoring for Slack Time Violation Without Performance Penalty" in 2018 IEEE International Symposium on Circuits and Systems (ISCAS), IEEE, May 2018. [DOI]
2. Shoba Gopalakrishnan and Virendra Singh, "REMORA: A hybrid low-cost soft-error reliable fault tolerant architecture" in 2017 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), IEEE, Oct. 2017. [DOI]
3. V S Vineesh, Nihar Hage, B Karthik, and Virendra Singh, "Achieving full functional coverage for the forwarding unit of pipelined processors" in 2017 IEEE East-West Design & Test Symposium (EWDTS), IEEE, Sep. 2017. [DOI]
4. Nihar Hage, Rohini Gulve, Masahiro Fujita, and Virendra Singh, "On Testing of Superscalar Processors in Functional Mode for Delay Faults" in 2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems (VLSID), IEEE, Jan. 2017. [DOI]
5. Rohini Gulve and Virendra Singh, "ILP based don't care bits filling technique for reducing capture power" in 2016 IEEE East-West Design & Test Symposium (EWDTS), IEEE, Oct. 2016. [DOI]
6. Shoba Gopalakrishnan and Virendra Singh, "REMO: Redundant execution with minimum area, power, performance overhead fault tolerant architecture" in 2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS), IEEE, Jul. 2016. [DOI]
7. Pawan Kumar and Virendra Singh, "Efficient regular expression pattern matching for network intrusion detection system using modified word-based automata" in 5th ACM International Conference on Security of Information and Networks, Jaipur, Oct. 2012.
8. Indira Rawat, M.K.Gupta and Virendra Singh, "Scheduling tests for 3D SOCs with temperature constraints" in 10th IEEE East West Design and Test Symposium 2012, Kharkov, Ukrain, Sep. 2012.
9. A.Matrosova, E.Nikolaeva, V.Singh and D.Kudin, "PDF testability of the circuits derived by special covering of ROBDDs with gates " in 10th IEEE East West Design and Test Symposium 2012, Kharkov, Ukrain, Sep. 2012.
10. A.Matrosova, S.Ostanin, A.Melnikov and V.Singh, "Observability calculation of state variable oriented to robust PDFs and LOC or LOF techniques" in 10th IEEE East West Design and Test Symposium 2012, Kharkov, Ukrain, Sep. 2012.
11. Indira Rawat, M.K.Gupta and Virendra Singh, "Thermal Aware Test Scheduling of 3D SOCs" in 5th IEEE International workshop on Impact of Low Power Designs on Test and Reliability, Annecy, France, Jun. 2012.
12. Suraj Sindia, Vishwani D, Agrawal, and Virendra Singh, "Impact of process variation on computers used for image processing" in IEEE International Symposium on Circuits and Systems (ISCAS) 2011, Seoul, Korea, May 2012.
13. Satdev Ahlawat, Virendra Singh, Shashidhar Bapat, and Karthik Madhugiri, "Low power scan flip-flop design to eliminate output gating overhead for critical paths" in IEEE International Workshop on Reliability Aware System Design and Test (RASDAT),Hyderabad, India, Jan. 2012.
14. Vijay Sheshadri, Prasanth V., Rubin Parekhji, Vishwani D. Agrawal, and Virendra Singh, "Evaluating impact of soft errors in embedded system" in IEEE International Workshop on Reliability Aware System Design and Test (RASDAT),Hyderabad, India, Jan. 2012.
15. Mohammed Shayan, Virendra Singh, Adit Singh, and Masahiro Fujita, "A highly robust and cost effective SEU tolerant memory cell" in IEEE International Workshop on Reliability Aware System Design and Test (RASDAT),Hyderabad, India, Jan. 2012.
16. Suraj Sindia, Vishwani Agrawal, and Virendra Singh, "Test and diagnosis of analog circuits using moment generating functions" in 20th IEEE Asian Test Symposium (ATS) 2011, New Delhi, India, Nov. 2011.
17. Mohammed Abdul Razzaq, Virendra Singh, and Adit Singh, "SSTKR: Secure and testable scan design through test key randomization" in 20th IEEE Asian Test Symposium (ATS) 2011, New Delhi, India, Nov. 2011.
18. Manas Puthal, Virendra Singh, MS Gaur and Vijay Laxmi, "C-Routing: An adaptive hierarchical NoC routing methodology" in 19th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) 2011, Hongkong, China, Oct. 2011.
19. Pramod Subramanyan, Virendra Singh, Kewal Saluja, and Erik Larsson, "Adaptive execution assistance for multiplexed fault-tolerant chip multiprocessors" in 29th IEEE International Conference on Computer Design (ICCD) 2011, Amherst, MA, USA, Oct. 2011.
20. Anzhela Matrosova, Virendra Singh, Alexey Melnikov, and Ruslan Mukhamedov, "Selection of state variables for partially enhanced scan" in 9th IEEE East-West Design and Test Symposium (EWDTS) 2011, Sevastopol, Ukraine, Sep. 2011.
21. Harsh Gidra, Israrul Haque, Nitin Kumar, M. Sargurunathan, M.S. Gaur, Vijay Laxmi, Mark Zwolinski, and Virendra Singh, "Parallelizing TUNAMI-N1 using GP-GPU" in 13th IEEE International Conference on High Performance Computing and communication (HPCC) 2011, Banff, Canada, Sep. 2011.
22. Mohammad Abdul Razzaq, Alok Baluni, Ram Rakesh Jangir, Virendra Singh, and Masahiro Fujita, "On synthesis of degradation aware circuits at higher level of abstraction" in 9th IEEE East-West Design and Test Symposium (EWDTS) 2011, Sevastopol, Ukraine, Sep. 2011.
23. Pawan Kumar and Virendra Singh, "Efficient regular expression pattern matching using cascaded automata architecture for network intrusion detection system" in 9th IEEE East-West Design and Test Symposium (EWDTS) 2011, Sevastopol, Ukraine, Sep. 2011.
24. V. Prasanth, Virendra Singh, and Rubin Parekhji, "Reduced overhead soft error mitigation methodology using error control coding technique" in 17th IEEE International On-Line Test Symposium (IOLTS) 2011, Athens, Greece, Jul. 2011.
25. A. Matrosova, S. Ostanin, A. Milnikov, and Virendra Singh, "Using AND-OR tree for path delay faults" in IEEE International Workshop on Processor Verification, Test and Debug (IWPVTD) 2011, Trondheim, Norway, May 2011.
26. Dimitar Nikolov, Urban Ingelsson, Virendra Singh, and Erik Larsson, "Study on level of confidence for rollback recovery with check-pointing" in Workshop on Dependability Issues in Deep-submicron Technologies (DDT) 2011, Trondheim, Norway, May 2011.
27. Suraj Sindia, Vishwani Agrawal, and Virendra Singh, "Nonlinear analog circuit test and diagnosisunder process variation using V-transform coefficients" in 29th IEEE VLSI Test Symposium (VTS), 2011, California, USA, May 2011.
28. Dimitar Nikolov, Urban Ingelsson, Virendra Singh, and Erik Larsson, "Level of confidence evaluation and its usage for roll-back recovery and checkpoint optimization" in Workshop on Dependable and Secure Nanocomputing (WDSN) 2011, Hongkong, China, May 2011.
29. Vinutha Konandur, Virendra Singh, MS Gaur, and Anzhela Matrosova, "Fault Grading at Higher Level of Abstraction" in IEEE International Workshop on Processor Verification, Test and Debug (IWPVTD) 2011, Trondheim, Norway, May 2011.
30. Sudipta Sarkar, Anubhav Adak, Virendra Singh, Kewal Saluja, and Masahiro Fujita, "SEU tolerant SRAM cell" in International Symposium on Quality Electronic Design (ISQED) 2011, Santa Clara, CA, USA, Mar. 2011.
31. Chao Han, Adit Singh, and Virendra Singh, "Efficient partial enhanced Scan for high coverage delay testing" in 2011 Joint IEEE International Conference on Industrial Technology and 43rd Southeastern Symposium on System Theory (ICIT-SSST) 2011, Auburn, USA, Mar. 2011.
32. Suraj Sindia, Vishwani Agrawal, and Virendra Singh, "Distinguishing process variation induced faults from manufacturing defects in analog circuits using V-transform coefficients" in 2011 Joint IEEE International Conference on Industrial Technology and 43rd Southeastern Symposium on System Theory (ICIT-SSST) 2011, Auburn, USA, Mar. 2011.
33. Naveen Choudhary, M.S. Gaur, Vijay Laxmi, and Virendra Singh, "Traffic aware topology generation methodology for application specific NoC" in IEEE International Symposium on Electronic Design, Test and Application (DELTA) 2011, Queens Town, New Zealand, Jan. 2011.
34. Navaneeth Rameshan, Mark Zwolinski, Vijay Laxmi, M.S. Gaur, Virendra Singh, and Lalith P., "Acceleration of functional validation using GPGPU" in IEEE International Symposium on Electronic Design, Test and Application (DELTA) 2011, Queens Town, New Zealand, Jan. 2011.
35. Dimitar Nikolov, Mikael Vayrynen, Urban Ingelson, Virendra Singh, and Erik Larsson, "Optimizing Fault Tolerance for Multi-Processor System-on-Chip" in Design and Test Technology for Dependable Systems-on-Chip, Editors: Raimund Ubar, Jaan Raik, Heinrich Theodor Vierhaus, 2010, Hardcover, ISBN:978-1-6096-0212-3. , Dec. 2010.
36. Jaynarayan Tudu, Erik Larsson, and Virendra Singh, "Test Scheduling of modular system-on-chip under capture power constraints" in 11th IEEE Workshop on RTL and High Level Test (WRTLT) 2010, Shanghai, China, Dec. 2010.
37. Sudipta Sarkar, Anubhav Adak, Virendra Singh, Kewal Saluja, and Masahiro Fujita, "SEU tolerant SRAM for FPGA application" in International Conference on Field Programmable Technology (FPT) 2010, Beijing, Dec. 2010.
38. Amit Mishra, Nidhi Sinha, Satdev, Virendra Singh, Sreejit Chakravarty, and Adit Singh, "A modified scan flip-flop for test power reduction" in 19th IEEE Asian Test Symposium (ATS) 2010, Shanghai, China, Dec. 2010.
39. Naveen Choudhary, M.S. Gaur, Vijay Laxmi, and Virendra Singh, "Energy Aware Design Methodologies for Application Specific NoC" in 28th Norchip Conference (NORCHIP), 2010, Tampere, Finland, Nov. 2010.
40. Vinay N.S, Indira Rawat, Erik Larsson, M.S. Gaur, and Virendra Singh, "Thermal aware test scheduling for stacked multi-chip modules" in IEEE East-West Design and Test Symposium (EWDTS) 2010, St. Petersburg, Russia, Sep. 2010.
41. Gayaprasad Sinsinwar, Rahul Choudhary, Aditi kajala, and Virendra Singh, "Test program generation for simultaneous testing of multiple identical functional units" in IEEE East-West Design and Test Symposium (EWDTS) 2010, St. Petersberg, Russia, Sep. 2010.
42. Anzhela Matrosova, Valeriy Lipsky, Aleksey Melnikov, and Virendra Singh, "Path delay faults and ENF" in IEEE East-West Design and Test Symposium (EWDTS) 2010, St. Petersburg, Russia, Sep. 2010.
43. Adit Kajala, Gayaprasad Sinsinwar, Rahul Choudhary, Jaynarayan Tudu, and Virendra Singh, "On selection of state variables for delay test of identical functional units" in IEEE East-West Design and Test Symposium (EWDTS) 2010, St. Petersburg, Russia, Sep. 2010.
44. K.R. Vinutha, Virendra Singh, Anzhela Matrosova, and M.S. Gaur, "Fault grading using instruction-execution graph" in IEEE East-West Design and Test Symposium (EWDTS) 2010, St. Petersburg, Russia, Sep. 2010.
45. Prasanth V., Virendra Singh, and Rubin Parekhji, "Robust detection of soft errors using delayed capture methodology" in IEEE International Online Testing Symposium (IOLTS) 2010, Corfu, Greece, Jul. 2010.
46. Pramod Subramanyan, Virendra Singh, Kewal K. Saluja, and Erik Larsson, "Energy ffficient fault tolerance in chip multiprocessors using critical value forwarding" in 40th IEEE International Conference on Dependable Systems and Networks (DSN), Chicago, IL, USA, Jun. 2010.
47. Abhishek A., Amanulla Khan, Virendra Singh, Kewal Saluja, and Adit Singh, "Test application time minimization for RAS using basis optimization of column decoder" in IEEE International Symposium on Circuits and Systems (ISCAS) 2010, Paris, France, May 2010.
48. Jaynarayan Tudu, Erik Larsson, Virendra Singh, and Hideo Fujiwara, "Scan cell reordering to minimize peak power during test cycle: A graph theoretic approach" in 15th IEEE European Test Symposium (ETS) 2010, Prague, Czech Rep., May 2010.
49. Pramod Subramanyan, Virendra Singh, Kewal K. Saluja, and Erik Larsson, "Power efficient redundant execution for chip multiprocessors" in Great Lake Symposium on VLSI (GLSVLSI) 2010, Providence, Rhode Island, USA , May 2010.
50. Raghavendra Adiga, Arpit Gandhi, Virendra Singh, Kewal Saluja, and Adit Singh, "Modified T-FF bases scan cell for RAS" in 15th IEEE European Test Symposium (ETS) 2010, Prague, Czech Rep., May 2010.
51. Dimitar Nikolov, Erik Karlsson, Urban Ingelsson, Virendra Singh, and Erik Larsson, "Mapping and scheduling of jobs in homogeneous NoC-based MPSoC" in 10th Swedish System-on-Chip Conference, Kolmarden, Sweden, May 2010.
52. Jaynarayan Tudu, Erik Larsson, Virendra Singh, and Hideo Fujiwara, "Graph theoretic approach for scan cell reordering to minimize peak shift power" in 20th ACM Great Lake Symposium on VLSI (GLSVLSI) 2010, Providence, Rhode Island, USA , May 2010.
53. Naveen Choudhary, MS Gaur, Vijay Laxmi, and Virendra Singh, "Genetic algorithm based topology generation for application specific network-on-chip" in IEEE International Symposium on Circuits and Systems (ISCAS) 2010, Paris, France, May 2010.
54. L. Suresh, N. Rameshan, A. Narayan, M. Zwolinski, M.S. Gaur, V. Laxmi, and V. Singh, "EDA design flow acceleration by GP-GPU" in 2nd Workshop on Designing for embedded parallel computing plateform: Architectures, design tools, and applications (in conjunction with DATE 2010) 2010, Dresden, Germany, Mar. 2010.
55. Pramod Subramanyam, Virendra Singh, Kewal Saluja, and Erik Larsson, "A low cost redundant execution architectures for Chip multiprocessors" in Design Automation and Test in Europe (DATE) 2010, Dresden, Germany, Mar. 2010.
56. Naveen Choudhary, MS Gaur, Vijay Laxmi and Virendra Singh, "Fast energy aware application specific network-on-chip topology generator" in IEEE International Advanced Computing Conference 2010, Patiala, India, Feb. 2010.
57. Suraj Sindia, Virendra Singh, and Vishwani D. Agrawal, "Parametric Fault Diagnosis of Nonlinear Analog Circuits using Polynomial Coefficients" in 23rd International Conference on VLSI Design (ICVD) 2010, Bangalore, Jan. 2010.
58. Dimitar Nikolov, Urban Ingelsson, Virendra Singh, and Erik Larsson, "On-line techniques to adjust and optimize checkpointing frequency" in IEEE International Workshop on Reliability Aware System Design and Test (RASDAT) 2010, Bangalore, India, Jan. 2010.
59. Raghavendra Adiga, Arpit Gandhi, Virendra Singh, Kewal Saluja, Hideo Fujiwara, and Adit Singh, "On Minimization of Test Application Time for RAS" in 23rd International Conference on VLSI Design (ICVD) 2010, Bangalore, Jan. 2010.
60. Dimitar Nikolov, Urban Ingelsson, Virendra Singh, and Erik Larsson, "Estimating error probability and its application for optimizing roll-back recovery with checkpointing" in IEEE Symposium on Electronic Design, Test & Applications (DELTA) 2010, Ho Chi Minh , Vietnam, Jan. 2010.
61. Naveen Choudhary, MS Gaur, Vijay Laxmi, and Virendra Singh, "Designing Application Specific Irregular Topology for Network-on-Chip" in 17th International Conference on Advanced Computing and Communications (ADCOM) 2009, Bangalore, Dec. 2009.
62. Naveen Choudhary, MS Gaur, Vijay Laxmi, and Virendra Singh, "Cojoined Irregular Topology and Routing Table Generation for Network-on-Chip" in IEEE INDICON 2009, Gandhi Nagar, India, Dec. 2009.
63. Jaynarayan Tudu, Erik Larsson, Virendra Singh, and Hideo Fujiwara, "Scan Cells Reordering to Minimize Peak Power during Scan Testing of SoC" in IEEE WRTLT, Hong Kong, Nov. 2009.
64. Suraj Sindia, Virendra Singh, and Vishwani Agrawal, "Multi-tone Testing of Linear and Nonlinear Analog Circuits using Polynomial Coefficients" in IEEE Asian Test Symposium (ATS), Taichung, Taiwan, Nov. 2009.
65. Deepak K.G., Robinson Reyna, Virendra Singh, and Adit Singh, "Leveraging Partial Enhanced Scan for Improved Observabilty in Delay Fault Testing" in IEEE Asian Test Symposium (ATS), Taichung, Taiwan, Nov. 2009.
66. Venkat Rajesh, Erik Larsson, MS Gaur, and Virendra Singh, "An Even Odd DFD Technique for Scan Chain Diagnosis" in IEEE WRTLT, Hong Kong, Nov. 2009.
67. Suraj Sindia, Virendra Singh, and Vishwani Agrawal, "V-Transform: An Enhanced Polynomial Coefficient Based DC Test for Non-linear Analog Circuits" in IEEE East-West Design and Test Symposium (EWDTS), Moscow, Russia, Sep. 2009.
68. Pramod Subramanyan, Ram Rakesh Jangir, Jaynarayan Tudu, Erik Larsson, and Virendra Singh, "Generation of Minimum Leakage Input Vectors with Constrained NBTI Degradation" in IEEE East-West Design and Test Symposium (EWDTS), Moscow, Russia, Sep. 2009.
69. Viney Kumar, Rahul Raj, and Virendra Singh, "FREP: A Soft-Error Resilient Pipelined RISC Architecture" in IEEE East-West Design and Test Symposium (EWDTS), Moscow, Russia, Sep. 2009.
70. Jaynarayan Tudu, Erik Larsson, Virendra Singh, and Adit Singh, "Capture Power Reduction for Modular System-on-Chip Test" in IEEE/VSI VLSI Design and Test Symposium (VDAT), Bangalore, India, Jul. 2009.
71. Suraj Sindia, Virendra Singh, and Vishwani Agrawal, "Bounds on Defect Level and Fault Coverage in Linear Analog Circuit Testing" in IEEE/VSI VLSI Design and Test Symposium (VDAT), Bangalore, India, Jul. 2009.
72. Pramod Subramanyan, Virendra Singh, Kewal K. Saluja, and Erik Larsson, "Power Efficient Redundant Execution for Chip Multiprocessor" in Workshop on Dependable and Secure Nanocomputing (WDSN), Lisbon, Portugal, Jun. 2009.
73. Suraj Sindia, Virendra Singh, and Vishwani D. Agrawal, "Polynomial Coefficient Based Multi-Tone Testing of Analog Circuits" in 18th IEEE North Atlantic Test Workshop (NATW), New York, USA, May 2009.
74. Jaynarayan Tudu, Erik Larsson, Virendra Singh, and Vishwani D. Agrawal, "On Minimization of Peak Power during SoC Test" in IEEE European Test Symposium (ETS), Seville, Spain, May 2009.
75. Reshma Jumani, Niraj Jain, Virendra Singh, and Kewal K. Saluja, "DX-Compactor: Distributed X-Compaction for SoC Test" in ACM Annual Great Lake Symposium on VLSI (GLSVLSI), Boston, USA, May 2009.
76. Suraj Sindia, Virendra Singh, and Vishwani Agrawal, "Coefficient-Based Parametric Testing of Non-Linear Analog Circuits" in ACM Annual Great Lake Symposium on VLSI (GLSVLSI), Boston, USA, May 2009.
77. Vinay NS, Erik Larsson, and Virendra Singh, "Thermal Aware Test Scheduling of Stacked Multi-Chip Modules" in Workshop on 3D Integration (In conjunction with DATE), Nice, France, Apr. 2009.
78. Mikael Vayrynen, Virendra Singh, and Erik Larsson, "Fault-Tolerant Average Execution Time Optimization for General Purpose Multi-Processor System-on-Chips" in Intl. Conference on Design Automation and Test in Europe (DATE), Nice, France, Apr. 2009.
79. Virendra Singh and Erik Larsson, "On Reduction of Capture Power for Modular System-on-Chip Test" in 9th IEEE WRTLT, pp. 35-40, Sapporo, Japan, Nov. 2008.

1. Ankit Jindal, Binod Kumar, Nitish Jindal, Masahiro Fujita, and Virendra Singh, "Silicon Debug with Maximally Expanded Internal Observability Using Nearest Neighbor Algorithm", IEEE, Jul. 2018.
2. "ATPG power guards: On limiting the test power below threshold", IEEE, Mar. 2018.
3. Rohini Gulve, Anshu Goel, and Virendra Singh, "PHP: Power hungry pattern generation at higher abstraction level", IEEE, Sep. 2017.